`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   22:50:42 01/24/2013
// Design Name:   ppiaddrmanager
// Module Name:   E:/ParaCPU/shaoxia-project/hdl/src/tb_modules/tb_ppiaddrmanager.v
// Project Name:  ise_ParaCPU
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: ppiaddrmanager
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module tb_ppiaddrmanager;

	// Inputs
	reg clk;
	reg rst_n;

	// Instantiate the Unit Under Test (UUT)
	ppiaddrmanager 
	#(.PP_NUM_LOG2(6))
	uut (
		.clk(clk), 
		.rst_n(rst_n)
		input [32*64-1:0] pps_wr_data,
input  [30*64-1]pps_wr_data_addr,
input [64-1:0] pps_wr_data_en,
output [64-1:0]pps_wr_data_consumed,
output reg [64-1:0] ext_ram_wr_en,
output  [32*64-1:0] ext_ram_wr_data,
output  [(30-EXT_RAM_BANKS_NUM_LOG2)*(2**EXT_RAM_BANKS_NUM_LOG2)-1:0] ext_ram_wr_addr,

input [2**PP_NUM_LOG2-1:0] pps_busy,
input sp_wr_en,
input [31:0] sp_wr_data,
input [31:2] sp_wr_addr,
output sp_wr_data_consumed
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		rst_n = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end
      
endmodule

